Floating gate memory devices such as flash memories include an array of electrically-programmable and electrically-erasable memory cells. Typically, each memory cell comprises a single n-channel metal oxide semiconductor (NMOS) transistor including a floating gate interposed between a control (input) gate and a transistor channel region. A layer of high-quality tunnel oxide used as gate oxide separates the transistor channel and the floating gate, and an oxide-nitride-oxide (ONO) dielectric stack separates the floating gate from the control gate. The ONO stack typically comprises a layer of silicon nitride (Si3N4) interposed between underlying and overlying layers of silicon dioxide (SiO2). The underlying layer of SiO2 is typically grown on the first doped polycrystalline silicon (polysilicon) layer. The nitride layer is deposited over the underlying oxide layer, and the overlying oxide layer can be either grown or deposited on the nitride layer. The ONO layer increases the capacitive coupling between the floating gate and the control gate, and reduces the leakage of current.
To program a flash cell, the drain region and the control gate are raised to predetermined potentials above a potential applied to the source region. For example 12, volts are applied to the control gate, 6.0 volts are applied to the drain, and 0.0 volts are applied to the source. These voltages produce “hot electrons” which are accelerated from the substrate across the gate oxide layer to the floating gate. Various schemes are used to erase a flash cell. For example, a high positive potential such as 12 volts is applied to the source region, the control gate is grounded, and the drain is allowed to float. More common erase bias conditions include: a “negative gate erase” in which −10V is applied to the control gate (Vg), 6V is applied to the source (Vs), a potential of 0V is applied to the body (Vbody), and the drain is allowed to float (Vd); and a “channel erase” which comprises a Vg of −9V, a Vbody of 9V, and a Vs and Vd of 9V or floating. In each case these voltages are applied for a timed period, and the longer the period the more the cell becomes erased. A strong electric field develops between the floating gate and the source region, and negative charge is extracted from the floating gate across the tunnel oxide to the source region, for example by Fowler-Nordheim tunneling.
In a flash memory device, the sources associated with each transistor within a sector are tied together, typically through the use of conductive doping of the wafer to form “source rails” which connect the sources of each transistor within a column. The columns within the sector are tied together using conductive plugs and a conductive line.
FIG. 1 depicts a cross section of transistors and other structures of a conventional flash electrically-erasable programmable read-only memory (E2PROM) device. Additional elements may be present in an actual device which are not depicted for simplicity of explanation. FIG. 1 depicts a semiconductor substrate assembly comprising a semiconductor wafer 10, transistor source 12 and drain 14 diffusion regions within semiconductor wafer 10, gate (tunnel) oxide 16, floating gates 18 typically comprising a first polysilicon layer, capacitor dielectric 20 typically comprising an oxide-nitride-oxide (ONO) stack, control gate (word line) 22 typically comprising a second polysilicon layer, a transistor stack capping layer 24 typically comprising silicon nitride (Si3N4) or tetraethyl orthosilicate (TEOS), oxide or nitride spacers 26, a planar dielectric layer 28 such as borophosphosilicate glass (BPSG), digit line plugs 30 connected to drain regions 14, and a conductive line 32 typically comprising aluminum which electrically couples each plug 30 within a row of transistors.
During the formation of a flash memory transistor, a sidewall oxidation is performed subsequent to forming the gate stack, and typically after implanting the source junction. This sidewall oxidation repairs any damage to the tunnel oxide which may occur during the etch which forms the transistor gate stack. The sidewall oxidation effectively increases the thickness of the tunnel oxide, and does so in a non-uniform manner. For example, during the sidewall oxidation the tunnel oxide thickens more near the exposed edges of the floating gate and decreases toward the center of the gate stack. Near the center of the gate stack the tunnel oxide retains its original thickness with no increase during the sidewall oxidation, as this portion of the tunnel oxide is not exposed to the oxidizing ambient. Because of the physical appearance, this non-uniform profile is commonly termed a “smile profile.”
The final profile resulting from the sidewall oxidation is dependent on the doping of both the polysilicon gate and that of the substrate. It is common for the doping of the source and drain regions to be different when this oxidation step occurs. Since the oxidation rate is sensitive to the doping of the substrate this will lead to a difference in the profile between the source and drain regions. When optimizing the performance of a flash cell, the thickening of the tunnel oxide over both of these regions is an important consideration. Since the source and drain regions have different functions in the operation of the flash cell, the ideal or optimized tunnel oxide profile over these junctions will also be different. Currently, if optimization of one aspect of the cell performance requires a change to the profile over one of the junctions, for example the source, then the profile over the drain junction will follow in lock step. The oxidation rate of the drain will be different from that of the source due to the different doping concentration, but the ratio of the oxidation of the source to the drain is fixed for fixed doping concentrations. For example, if the oxidation target is increased by 20% for one side, there will be a similar increase of about 20% on the other side. When trying to optimize many performance aspects of the memory cell, this fixed relationship requires that trade-offs be made to reach an acceptable balance between improving some parameters and degrading others. For example, the gate oxide must be sufficiently thin on the drain side to allow electrons to pass from the drain to the floating gate during programming, but must be thick enough on the source side such that erase characteristics and resistance to leakage of a charge from the floating gate to the wafer are optimized.
Various methods and structures have been used which affect the arrangement of the source, drain, channel, and gate oxide. U.S. Pat. Nos. 5,192,872 and 5,604,366, both by Lee and assigned to Micron Technology, Inc., describe two such arrangements and are incorporated herein by reference as if set forth in their entirety.
The oxidation rate of silicon is affected by the type and concentration of dopants implanted in the silicon. For example, U.S. Pat. No. 4,409,723 describes that thermal oxidation rates over a heavily doped N+ region can be several times higher than the oxidation rate over a lightly P-doped region. U.S. Pat. No. 5,382,534 describes that the oxidation rate of doped silicon is from two to four times as fast as the rate for undoped silicon. Further, U.S. Pat. No. 6,251,751 describes an increasing silicon oxidation rate as the boron concentration increases.
A method for forming a local interconnect for a semiconductor device, and an inventive structure resulting from the method, which reduces or eliminates the problems described above by allowing variable oxidation ratio of two regions with different but fixed doping concentrations would be desirable.